Design and Analysis of Low Power Back-gated Cntfet Sram Memory Cell Operating in Sub Threshold Region

While designing supporting and peripheral circuits like address decoders, sensing circuits, sensing amplifiers, pre charge and I/O control circuits are very important for the proper functioning of SRAM. BL and BL are the two access lines present in the SRAM memory cell which is accessed by the supporting circuits. Designing memory cell with low power consumption and high noise margin without compromising propagation delay is a very challenging engineering. In order to maintain performance, however, this has required a corresponding reduction in the transistor threshold voltage. The previous papers deal with memory cell designing using the CNTFET threshold region. By introducing body bias for the transistors, the power and the other characteristics of the memory is changed. This work explains with low supply voltage compared other works of CNTFET SRAM operating in sub threshold region.